\doxysection{FMC\+\_\+\+Bank5\+\_\+6\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_f_m_c___bank5__6___type_def}{}\label{struct_f_m_c___bank5__6___type_def}\index{FMC\_Bank5\_6\_TypeDef@{FMC\_Bank5\_6\_TypeDef}}


Flexible Memory Controller Bank5 and 6.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_c___bank5__6___type_def_a252c4ada37ac883b8e4fe0b08c781d0b}{SDCR}} \mbox{[}2\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_c___bank5__6___type_def_a8438638391415aaa0dc96714f28915ae}{SDTR}} \mbox{[}2\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_c___bank5__6___type_def_ad328f49a71561cd3f159af6faf65a641}{SDCMR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_c___bank5__6___type_def_ac1887d031d16c1bf2c0a51ee9001f886}{SDRTR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_c___bank5__6___type_def_a9f268f86cf706c2c78d8a6a9fbe9d9a3}{SDSR}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Flexible Memory Controller Bank5 and 6. 

\label{doc-variable-members}
\Hypertarget{struct_f_m_c___bank5__6___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_f_m_c___bank5__6___type_def_ad328f49a71561cd3f159af6faf65a641}\index{FMC\_Bank5\_6\_TypeDef@{FMC\_Bank5\_6\_TypeDef}!SDCMR@{SDCMR}}
\index{SDCMR@{SDCMR}!FMC\_Bank5\_6\_TypeDef@{FMC\_Bank5\_6\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SDCMR}{SDCMR}}
{\footnotesize\ttfamily \label{struct_f_m_c___bank5__6___type_def_ad328f49a71561cd3f159af6faf65a641} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMC\+\_\+\+Bank5\+\_\+6\+\_\+\+Type\+Def\+::\+SDCMR}

SDRAM Command Mode register, Address offset\+: 0x150 \Hypertarget{struct_f_m_c___bank5__6___type_def_a252c4ada37ac883b8e4fe0b08c781d0b}\index{FMC\_Bank5\_6\_TypeDef@{FMC\_Bank5\_6\_TypeDef}!SDCR@{SDCR}}
\index{SDCR@{SDCR}!FMC\_Bank5\_6\_TypeDef@{FMC\_Bank5\_6\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SDCR}{SDCR}}
{\footnotesize\ttfamily \label{struct_f_m_c___bank5__6___type_def_a252c4ada37ac883b8e4fe0b08c781d0b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMC\+\_\+\+Bank5\+\_\+6\+\_\+\+Type\+Def\+::\+SDCR\mbox{[}2\mbox{]}}

SDRAM Control registers , Address offset\+: 0x140-\/0x144 \Hypertarget{struct_f_m_c___bank5__6___type_def_ac1887d031d16c1bf2c0a51ee9001f886}\index{FMC\_Bank5\_6\_TypeDef@{FMC\_Bank5\_6\_TypeDef}!SDRTR@{SDRTR}}
\index{SDRTR@{SDRTR}!FMC\_Bank5\_6\_TypeDef@{FMC\_Bank5\_6\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SDRTR}{SDRTR}}
{\footnotesize\ttfamily \label{struct_f_m_c___bank5__6___type_def_ac1887d031d16c1bf2c0a51ee9001f886} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMC\+\_\+\+Bank5\+\_\+6\+\_\+\+Type\+Def\+::\+SDRTR}

SDRAM Refresh Timer register, Address offset\+: 0x154 \Hypertarget{struct_f_m_c___bank5__6___type_def_a9f268f86cf706c2c78d8a6a9fbe9d9a3}\index{FMC\_Bank5\_6\_TypeDef@{FMC\_Bank5\_6\_TypeDef}!SDSR@{SDSR}}
\index{SDSR@{SDSR}!FMC\_Bank5\_6\_TypeDef@{FMC\_Bank5\_6\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SDSR}{SDSR}}
{\footnotesize\ttfamily \label{struct_f_m_c___bank5__6___type_def_a9f268f86cf706c2c78d8a6a9fbe9d9a3} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMC\+\_\+\+Bank5\+\_\+6\+\_\+\+Type\+Def\+::\+SDSR}

SDRAM Status register, Address offset\+: 0x158 \Hypertarget{struct_f_m_c___bank5__6___type_def_a8438638391415aaa0dc96714f28915ae}\index{FMC\_Bank5\_6\_TypeDef@{FMC\_Bank5\_6\_TypeDef}!SDTR@{SDTR}}
\index{SDTR@{SDTR}!FMC\_Bank5\_6\_TypeDef@{FMC\_Bank5\_6\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SDTR}{SDTR}}
{\footnotesize\ttfamily \label{struct_f_m_c___bank5__6___type_def_a8438638391415aaa0dc96714f28915ae} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMC\+\_\+\+Bank5\+\_\+6\+\_\+\+Type\+Def\+::\+SDTR\mbox{[}2\mbox{]}}

SDRAM Timing registers , Address offset\+: 0x148-\/0x14C 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
